This guide assumes you have basic knowledge of capacitive sensing and you are familiar with the SENSE environment. If you feel that you are missing any of the necessary concepts or you are a new SENSE user, you may want to read the following articles that will help you get started:

IMPORTANT: We recommend that you try the example projects that can be found in your Project library to get acquainted with SENSE.

Introduction

When you first start designing your project, PCB or CAD design tools accompany you with design rules for your track or trace routing. Many times the traces are generated automatically following specific instructions, that are most of the time generic to cover all the different applications that have traces.

A design rule checker will focus on the 4 basic geometrical characteristics of the trace:

  • Trace width
  • Trace length
  • Trace clearance
  • Trace path

The design rules assist in enhancing the signal integrity or the power integrity of the electronics system. However, in a touch sensor application those trace rules will not take into account their influence and importance on the touch sensor performance.

In this report, we are going to focus on how the trace design influences the performance of our touch sensor and present a few ways to quantify this influence.

Setup up the sensor model in SENSE

To do that, we will create a virtual touch sensor in SENSE following a few simple steps:

  1. Prepare a .dxf file. Each conductive layer should be placed in a different CAD Layer / Prepare the gerber file of your design.
  2. Import it in SENSE. Assign each conductive layer to the corresponding Element in SENSE.
  3. Place the touchscreen in the Canvas of SENSE. Make sure you have imported the Οutline as well.
  4. Alternatively to steps 1-3, you can create the whole screen through SENSE Library.
  5. Create the StackUp of your touchscreen by assigning the thickness and the relative permittivity of your dielectrics and the sheet resistance of your conductors.

For our test we want to focus on the influence of the traces so we are going to use a standard sensor design and alter the trace design and path.

In order to have a metric of how the traces influence the performance, we will simulate the self capacitance of the 5 buttons shown in Figure 2, without any traces at all.

This is a test that generally cannot be replicated in the laboratory and only simulation can do it, but it is also rather important, since the touch sensor design rules discuss how a sensor’s shape and size should be but cannot take into account how the traces will interact with it.

So now we have the opportunity to test both.

Trace design rules and touch sensor design rules

In Figures 1 to 3 is the model of the sensor. It is a self capacitive button, maintaining good distances between the active electrodes to make sure that the position of the pointer touching can be pinpointed easily by the IC software. Furthermore, no irregular shapes are being used and any sharp edges are being smoothened to avoid high electrical fields in those areas that are common causes for dielectric breakdowns. In the end we want to produce the sensor of Figure 1, so we install electrodes just under the areas we want to activate, following the same shape.

Fig. 1. Sensor User Interface

Fig. 2. Top view of sensor layout

Fig. 3. Stack up of sensor

Fig. 4. 3D model of sensor

Let’s now try to figure out how we can test all 4 design rule checker geometrical characteristics of the trace. We can split them into two tests.

In the first test, we are going to showcase the influence of the length and path of the traces, when their width and clearance remain the same. For this reason, we are going to change the length of the traces, redraw their starting point and their ending point and measure how the self capacitance changes. Below is an example of how those changes can look like:

Fig. 5. Different lengths and paths

Then, in a second test, we are going to keep the same length and path but change width and clearance. In the three figures below we can see that the traces have 0.1, 0.15 and 0.2 mm width respectively. Here is how the traces can be drawn, with different widths (resulting in different clearances).

Fig. 6. Different widths and clearances


Simulation results

There are a plethora of different investigations that can now be made in order to understand how all those different designs operate.

The baseline investigation that should be performed, however, is that of the extraction of the self capacitance of the buttons when no pointer is touching the sensor. This value is a good indication of where we should focus next. It is expected that all buttons should have a self capacitance within IC limits, otherwise the reading of the controller will not be correct. So this is where we can start from.

For example, Microchip recommends, in their guide of QT60160 and QT60240 controllers, that the self capacitance of the buttons should be 2 to 20 pF. Similar limitations stand true in all controller families, so the designer should take them into account as well. No proper trace design can very easily load the touch sensor with parasitics, increasing the baseline self capacitance to a point that the sensor doesn’t work with specific controllers anymore.

Fig. 7. Self capacitances in pF without traces

Fig. 8. Self capacitances in pF for the different lengths and paths

Fig. 9. Self capacitances in pF for the different widths and clearances

What we observe from the capacitance results of SENSE is that even with this simple design with short traces length and not heavy coupling with shielding entities and parasitic elements, adding traces will load the design with much larger self capacitance.

Specifically, from Figure 8 we can see that the longer the traces the larger the self capacitance.

While, from Figure 9 we can see that the wider the traces the larger the self capacitance.

Those conclusions are of course well known among layout designers, here however we can quantify them instead of relying on rules and good practises and remain on the safe side.

A second investigation we can perform is to touch all the buttons exactly in their middle point. This is where the user interface designer expects the user to touch and the performance should be optimal there. For that example, we are going to test the final sensor design with 0.2 mm width of traces.

Fig. 10. Pointer - Sensor configuration

A very common pointer for those types of investigations is a simple cylinder, with 20 mm height and 10 mm diameter. It should be assigned as conductive in the settings of SENSE. The test can, of course, be replicated adding a covering material (i.e. glove) or setting a cylinder with hemispherical tip to represent a more “soft” touch.

Fig. 11. Pointer for the self capacitance test

The problem we expect to encounter by touching with our pointer over the sensor area is a change of self capacitance that is not large enough to be registered as a touch from the controller. This is caused many times because traces are so strongly coupled together or with parasitic elements that any change of the self capacitance is so small that it can be rejected by the controller. Most guides suggest at least 2 pF added to the self capacitance that safely registers as a touch event by the majority of the IC packages.

On the other hand, a very large change of capacitance can render a sensor too sensitive or outside the controller limits.

Let’s observe how the capacitances change with the presence of a pointer.

Table. 1. Self capacitances in pF after pointer touch


Conclusions

First of all, we have a very big self capacitance change. Although this is what we want in principle, it is also something that we try to avoid. In this case, a redesign of the electrodes and trace configuration is suggested to move all self capacitances within the 2-20 pF limit (borrowing the values from the previous Microchip guide)

Secondly, we observe a change of capacitance of ~12 pF for the Centre button, ~17 pF for the Left and Right ones and ~21 pF for the Top and Bot ones. Knowing those values is a great guide to connect the traces to corresponding PINS of the controller or to appropriate charging capacitors Cs as one can read here.

Finally, those findings can be combined with the resistance values of each electrode + trace couple. Since traces add capacitance and resistance and the time constant τ (= R*C) affects performance of the controller (charging time of each electrode), the proper design of the traces is always a trade off between the different effects. A trace designed to reduce Capacitance would most likely increase the Resistance.

To see how to design a best trade off between Capacitance and Resistance, maintaining all the rules a design rule checker requires, please have a look at our webinar.

Did this answer your question?